Prints area estimates on the screen after initial compilation.Ĭonverts all warning messages into error messages. The value must be an unsigned integer, and by default, the value is 1.ĭefines a preprocessor macro named macro_name.įPGA backend generates a verbose output describing the progress of the compilation. Sets the seed used by the Intel® Quartus® Prime software when generating the FPGA bitstream.
If it returns error code 42, the design failed to fit or meet timing. To see if the design fits and meets timing, you can check the error code of the icpx command. In SYCL, use the -Xsseed= option to change the seed and run multiple compiles yourself while changing the seed value ( n) for each compile. The -high-effort flag in OpenCL simply reruns the Intel® Quartus® Prime software compilation up to three times with different seeds to fit the design and meet timing. Refer to the FPGA BSPs and Boards section in the Intel oneAPI Programming Guide for additional details. If omitted, the compiler chooses the default FPGA target and variant, which are installation dependent. In SYCL, it specifies the FPGA target and variant. In SYCL, specifies the output executable name. In OpenCL, specifies the name of the output.
Instructs the compiler to stop after creating the FPGA early image and the associated optimization report.Īdds a directory to the list of directories that the compiler searches for header files during kernel compilation. Compiles your kernel and generates the output of the parser without creating an FPGA programming image file.
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